1. Field of the invention
The present invention relates generally to a microcomputer, and more particularly, to a clock generating circuit capable of continuing to generate clocks even if a "runaway" occurs in a central processing unit (CPU) included in the microcomputer, thereby keeping the microcomputer operative.
2. Description of Related Art
In order to avoid the consumption of electricity when the operation of a microcomputer is not necessary, most microcomputers (microcontrollers) built in the electronic apparatus are so devised as to stop the oscillation of clocks and keep themselves inoperative. In general, such clock oscillation stoppage is effected in response to a signal outputted by the CPU (central processing unit).
FIG. 1 is a block diagram showing the configuration of a typical example of the known clock generating circuits provided in microcomputers. In FIG. 1, there is provided a clock generating circuit 5 (hereinafter called "clock generator 5") which includes a clock oscillator 23 oscillated by a ceramic resonator 36. The ceramic resonator 36 is connected to load capacitances C1 and C2 whose other ends are earthed. The junction between the ceramic resonator 36 and the load capacitance C2 is connected to a clock output terminal Xout, and the junction between the ceramic resonator 36 and the load capacitance C1 is connected to an input terminal of an NAND circuit 37 of an clock oscillator 23, and an output terminal of the NAND circuit 37 is connected to the clock output terminal Xout through a damping resistor R. The ceramic resonator 36 provides a positive feed back to the NAND circuit 37.
In addition to the clock oscillator 23, the clock generator 5 includes an R-S flip-flop 35 and a clock oscillation request signal generating division 15 (hereinafter referred to as "division 15"). The other input terminal of the NAND circuit 37 is connected to the output terminal Q of the R-S flip-flop 35. An input terminal S of the R-S flip-flop 35 is connected to the division 15 which generates a clock oscillation request signal in response to the reception of any one of clock oscillation request signals 12a to 12c from outside the microcomputer 1 or a clock oscillation request signals 13a to 13c from inside it. An input terminal R of the R-S flip-flop 35 is connected to a data bus DB of the microcomputer 1.
There is provided a frequency divider 4 which divides the frequency of an oscillating voltage outputted through the clock output terminal Xout to a frequency inherent in the microcomputer 1, and is inputted to the CPU 2. The CPU 2 exchanges data with the memory 3 and peripheral devices through the data bus DB in synchronism with the clock frequency, and arithmetically processes the data.
The clock generator 5 and the microcomputer 1 are operated as follows:
In response to the reception of any one of the clock oscillation request signals 12a to 12c from outside the microcomputer 1 or the clock oscillation request signals 13a to 13c from inside the microcomputer 1, the division 15 inputs a clock oscillation request signal "1" to the input terminal S of the R-S flip-flop 35. In this way the output terminal Q of the R-S flip-flop 35 is ready to output a signal "1".
As a result, the NAND circuit 37 and the damping resistor R provide a voltage to the ceramic resonator 36, wherein the voltage has a resonance frequency inherent in the ceramic resonator 36, thereby maintaining the resonance motive voltage occurring in the ceramic resonator 36. The frequency divider 4 divides down this resonance voltage to a clock frequency inherent in the microcomputer 1 which is then inputted to the CPU 2 to operate it.
When the operation of the microcomputer 1 becomes unnecessary, the CPU 2 executes a clock oscillation stop order OP 1 stored in the memory 3, and inputs a clock oscillation stop signal "1" to the input terminal R of the R-S flip-flop 35 through the data bus DB. In this way the output terminal Q of the R-S flip-flop 35 is ready to output "0".
As a result, the output of the NAND circuit 37 becomes "1" and is stabilized, thereby stopping the resonance of the ceramic resonator 36. Because of having no supply of clocks to the CPU2, the microcomputer 1 stops.
If a "runaway" or malfunction of the CPU 2 occurs, the CPU 2 is in danger of executing a non-top address as a top address or executing any data in a non-assigned area as if it is an assigned program in an assigned area. Once such a malfunction occurs, the CPU tends to behave in unforeseen manner. If the data area should contain a similar code data to the clock oscillation stop order OP 1, the CPU 2 will execute the wrong data as the clock oscillation stop order OP 1. As a result, the supply of clock is stopped. Once a "runaway" occurs in the CPU 2 to result in the discontinuation of microcomputer operation, this unwanted situation is likely to continue permanently.
In order to solve the problems discussed above, there are proposals which are disclosed in Japanese Patent Application Laid-Open Publication Nos. 3-148731 (1991) and 5-181697 (1993). The former relates to a clock generator which can stop the oscillation of clocks only when the clock oscillation stop order is executed at a particular limited circumstances such as when the first signal after resetting is an enabling signal. The latter relates to a clock generator which stops the generation of clock pulses in a case where an unexpected error occurs while an error test program is executed. Another proposal is disclosed in Japanese Patent Application Laid-Open Publication No. 5-35530 (1993), relating to a clock generator which executes an address stop at the desired address where the clocks are to be stopped, under the condition whether the order in designated address should execute or not. Another proposal is disclosed in Japanese Patent Application Laid-Open Publication No. 5-224966 (1993), relating to a clock generator which permits the execution of a clock stop order only when the clock stop order is found to be valid by comparison to the predetermined requirement for validity or invalidity.